As MOS devices have been integrated at a rapid speed, an existing process using polysilicon as a gate electrode has caused many problems such as high gate resistance, depletion of polysilicon, and boron penetration into a channel area. Such problems have been solved by a process including a metal gate electrode. However, the process of forming a metal gate has caused new problems, such as difficulty in etching a metal and limitations in enduring high-temperature thermal treatment.
Accordingly, a damascene process has been proposed to solve such problems. However, the damascene process uses a chemical mechanical polishing (CMP) process repeatedly, thereby complicating the process, although CMP solved the problems of an existing metal gate process.
To obviate such process complexity, a method of making a MOS transistor using a single CMP process has been proposed. Reference will now be made in detail to a known MOS transistor fabricating method using a single CMP process, examples of which are illustrated in the accompanying drawings. FIGS. 1a through 1c are cross-sectional views illustrating a MOS transistor fabricated according to a known process. Referring to FIG. 1a, a polysilicon gate electrode 5 is formed on a semiconductor substrate 1, and lightly doped drain (LDD) regions 2 are formed on the substrate 1 at both sides of the polysilicon gate electrode 5. Then, a spacer 6 is formed on both lateral walls of the polysilicon gate electrode 5, and source and drain regions 3 are formed on the substrate 1 at both sides of the polysilicon gate electrode 5. Subsequently, a silicide layer 7 is coated on the top of the polysilicon gate electrode 5 and the surface of the source and drain regions 3, and a nitride layer 8 is formed on the entire area of the semiconductor substrate having the source and drain regions 3 and the LDD regions 2 so that the polysilicon gate electrode 5 can be covered. Next, an insulating layer 9 is formed on the nitride layer 8. The nitride layer 8 is usually between about 300 and about 1000 Å in thickness, and is formed by a plasma enhanced chemical vapor deposition (PECVD) process.
Next, referring to FIG. 1b, the nitride layer 8 and the insulating layer 9 are polished by a CMP process until the top of the polysilicon gate electrode 5 is exposed. The CMP process is performed by over polishing so that the top of the polysilicon gate electrode 5, in uniform thickness, can be exposed completely. Then, a metal layer 10 is deposited, in uniform thickness, on the exposed region of the polysilicon gate electrode 5, the nitride layer 8 and the insulating layer 9. The metal layer 10 is usually less than about 1000 Å and, in some cases, may be between about 500 and about 1000 Å in thickness. The metal layer 10 may be a multilayer of Ti/TiN, Co/TiN, or Co/Ti/TiN.
Referring to FIG. 1c, a thermal treatment is performed on the substrate having the metal layer 10 to transform the polysilicon gate electrode 5 into a metal silicide gate electrode 7. The thermal treatment process may be performed through two steps, i.e., a first step at a temperature of about 400° C. to about 600° C., and a second step using a rapid thermal process (RTP) at a temperature of about 800° C. to about 1000° C. Subsequently, the residual metal layer, which has not reacted, is removed.
However, such a method of fabricating a MOS transistor cannot completely transform the polysilicon gate electrode 5 into the metal silicide gate electrode 7 because the area where the metal of the metal layer can be diffused while performing the thermal treatment is insufficient due to the small contact area between the polysilicon gate electrode 5 and the metal layer 10. To obviate such a disadvantage, the thermal treatment process to form the metal silicide gate electrode 7 has to be performed for many hours. However, such a long thermal treatment may cause deterioration of device characteristics because an impurity implanted in source and drain regions 3 may be diffused irregularly.